Intel has completed a $3 billion expansion of its Oregon-based research semiconductor facility, dubbed D1X. The new clean rooms provide an area of a good 250,000 square meters and are built higher than before so that larger exposure machines will fit in in the future, which Intel and other chip manufacturers such as TSMC or Samsung will need from 2025.
It is about systems that expose silicon wafers with extreme ultraviolet wavelengths at a high numerical aperture (high-NA EUV) of 0.55 instead of 0.33. Intel wants to use them from 2025 in the third process from the coming Angstrom era.
ASML from the Netherlands is the only manufacturer that can supply such exposure machines in the foreseeable future. In high-NA systems, he uses larger mirrors and lenses – such as those from the German manufacturer Zeiss – with steeper refractive angles to refine the resolution from 13 to 8 nanometers. This enables chip manufacturers to achieve finer transistor structures in a single exposure step.
High NA systems are larger than previous EUV imagesetters. Due to the height, they do not fit into old clean rooms.
First at High NA
For an early start, Intel has contractually secured the first high NA system from ASML. From 2025, this EXE:5200 exposure machine will process 220 silicon wafers per hour in the D1X factory – exposing one layer at a time. The problem that the first EUV systems were too slow for series production should be solved. If the new manufacturing technology proves its worth in the D1X plant, Intel will upgrade its global manufacturing sites. New semiconductor factories like the one in Magdeburg are being built directly with High-NA in mind.
With the first delivery, Intel has a head start over TSMC, Samsung and other chip manufacturers. Traditionally, ASML only delivers a handful of coveted new exposure machines from a completely new generation in the first year and then scales up production. A current EUV imagesetter already costs almost 150 million euros; ASML sold 42 units in 2021.
From 2025, Intel wants to provide the best manufacturing process with the highest performance per watt. A year earlier, the first Angstrom processes (20A and 18A) should catch up with TSMC, which should be able to manufacture with its own N2 process. At the beginning of 2020, Intel had planned to catch up with the competitor with the Intel 3 process – called 5 nm at the time – before there were further delays.
Intel has set itself ambitious goals: process parity with TSMC from 2024, leadership from 2025.
Evasion processes for technology delays
In order to absorb possible delays in the future better than before – remember the years of fiasco surrounding the 10 nm process (now called Intel 7) – Intel is preparing alternative plans at an early stage. If the first production process from the Angstrom era, 20A, is not ready by 2024 as planned, Intel can switch to a so-called "Intel Risk Reduction Test Node", which introduces the new power vias but not yet the RibbonFET design.
An updated overview of Intel's planned manufacturing processes: The "Intel Risk Reduction Test Node" serves as a plan B in case the 20A process is delayed.
Power vias conduct the current from the bottom of the chip to the transistor level instead of from above, which should significantly improve signal quality and reduce crosstalk between individual lines. RibbonFETs are Intel's version of the FinFET successor technology Gate All Around (GAA), in which the conductive channel of the field effect transistor (FET) is surrounded on all sides by the gate electrode. Intel already introduced FinFETs with the 22 nm generation.
A generation later, Intel is not necessarily dependent on the high-NA imagesetters: the company can also expose the corresponding layers with the previous system – that is not optimal, but a worse product is better than none at all.